In recent years, as mobile equipment has developed, a reduction in power source voltage has been sought in order to reduce the power consumption of an LSI. However, the operation lower limit voltage (VDDmin) of the SRAM cannot be lowered because the variation in the threshold value of the memory cell of the SRAM increases due to the miniaturization of an LSI. This prevents further decrease in the power source voltage.
Therefore, a dual rail method has been adopted in which power sources of different voltages are supplied to the memory cell array portion of the SRAM and to the other portion, respectively. An LSI chip mounting a dual-rail SRAM mounts a power source voltage generation circuit configured to generate a first power source that has a first voltage value and which is supplied to the portion other than the memory cell array portion of the SRAM, and a second power source having a second voltage value greater than the first voltage value from the first power source. There is a case where a power source supplied from outside the chip is used as it is as the first power source. The power source voltage generation circuit is implemented by a charge pump or the like. Mounting the power source voltage generation circuit is a factor in increasing the area of the LSI chip.
The dual-rail SRAM has the memory cell array portion and the other circuit portion. The memory cell array portion includes a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells arranged in correspondence to the intersection portions of the plurality of word lines and the plurality of bit line pairs, a plurality of column switch pairs, a sense amplifier, a write amplifier, a bit line precharging circuit, etc. The other circuit portion includes a row decoder, a column decoder, a control circuit, an I/O circuit, etc.
The dual-rail SRAM has a power down (PD) mode in which the supply of power source to the portion other than the memory cell of the memory cell array portion is stopped when the read or write operation is not performed in order to further reduce power consumption.
In the dual-rail SRAM, when the normal operation in which the read operation or write operation is performed ends and when the power down mode ends, a precharging operation to charge a bit line pair BL/BLX, whose level has dropped, to the second voltage value is performed. The power source voltage generation circuit supplies a current to charge the bit line pair BL/BLX to the second voltage value at the time of the precharging operation. At the time of the precharge of the bit line pair BL/BLX, if a sufficient current is not supplied from the power source voltage generation circuit (charge pump circuit), the second voltage value of the second power source will drop. The second power source is also supplied to the memory cell array portion and if the second voltage value drops, there is a possibility that the contents stored in the memory cell will be lost. Consequently, the power source voltage generation circuit (charge pump circuit) is required to have a current supply capacity equal to or higher than a certain level, and therefore, it is not possible to reduce the circuit area.